The present invention relates to an information recording/reproducing apparatus, such as a magnetic disk apparatus and a magneto-optic disk apparatus, and a signal processing circuit used in those apparatuses, and more particularly to a circuit and a method for optimizing coefficients of an equalizer circuit having functions of estimating a detection or discrimination performance in optimization of the equalizer circuit, and optimization of various conditions in recording and reproduction, such as the write current value, DC offset compensation amount, etc, in apparatuses involving a partial response processing.
In an information recording/reproducing apparatus of this kind, it is necessary to optimally set various control parameters for recording and reproducing signals. To give an example, the optimization of the write current value in a magnetic disk apparatus is performed as follows. A write current value is set and recorded on a magnetic disk, then the bit error rate (BER) is measured while varying the phase of the discrimination window of the phase discriminator, which is a detection circuit of the reproduced signal processing circuit, to measure the phase width (phase margin) of the discrimination window which provides a tolerable level of BER (e.g., 1.0Exe2x88x928 or less). FIG. 2 shows a so-called bucket curve. This measurement is performed each time the write current value is changed, and the phase margins at various write current values are obtained. As shown in FIG. 3, the relation between write current values and the corresponding phase margins are checked and the write current value at which the phase margin is greatest is taken as the optimum value.
In evaluation of the BER in an apparatus of phase discrimination system of this kind, in order to obtain a bucket curve as shown in FIG. 2, a length of time at least in the order of minutes is required. It follows therefore that several minutes are required only to perform the optimization of the write current mentioned above.
In an actual optimization process, in addition to the write current value, other optimization parameters include the compensation amount (in what is referred to as write pre-compensation) of the flux reversal positions of the write current, equalizer circuit characteristics and detection levels of the error detector. More importantly, since those parameters are evaluated using a random pattern, they cannot be evaluated independently of each other. For this reason, in order to optimize the parameters with high accuracy, measurement of the bucket curve is preferably performed as many times as the product of the number of parameters and the number of partitions of the parameters, so that a vast length of time is required for the whole optimization process. If there are great variations among the magnetic heads and the recording/reproducing circuits, it is necessary to perform this optimization process for individual apparatuses and magnetic heads, so that a much greater length of time is required.
In evaluation of the BER by amplitude detection system, on the other hand, the technique disclosed in JP-A-3-144969 is well known. This method is such that a sequence of digital signals input to the detector of the apparatus are compared with a sequence of reference signals to measure a histogram of error values to thereby estimate a BER of the apparatus. The number of bits required to measure the histogram with high accuracy is on the order of thousands or tens of thousands at most, and this number is far smaller than one in the above-mentioned case (1.0E+8 bits or greater) using the phase detection system which measures the BER directly, and hence the time required to optimize the parameters is much shorter.
In the evaluation based on the estimation of the BER in the apparatus of amplitude discrimination system revealed in JP-A-3-144969, however, a relatively large scale evaluation device is required for measuring a histogram of error values. It is required to determine error values in real time and install counters or memories as many as the number of the histograms measured. If this measurement of the histograms is made inside the apparatus, an increase in the scale of the circuit is inevitable. If histograms are measured outside the apparatus while monitoring the input signal of the detector on the circuit board, measurement has to be performed at the bit rate of the apparatus, which poses a great difficulty in mounting or packaging the measuring apparatus in the case of an apparatus adapted to operate at high data transmission rate exceeding 100 Mbps.
With regard to the technique of optimizing the tap coefficients of an equalizer circuit, there is a method disclosed in JP-A-2-150114. In this publication, looking at the fact that the reproduced waveform (so-called solitary magnetization reproduced waveform) which corresponds to a single flux reversal or magnetization reversal in an information recording/reproducing apparatus such as a magnetic disk apparatus or a magneto-optic disk apparatus is a waveform that has the leading and trailing foot portions formed substantially so symmetrically as to be simulated by a Lorentzian waveform, there are proposed coefficient compensation means and a method of a transversal type equalizer circuit with symmetric coefficients at three taps, in other words, a so-called cosine equalizer circuit, wherein in a format on the magnetic disk, a training area of several bytes is provided before user data to perform coefficient compensation in real time.
In a case where only one tap coefficient is to be optimized as in a cosine equalizer circuit, it is preferable to use the method disclosed in JP-A-2-150114 mentioned above. However, if data is to be recorded with high density, the resolution of the reproduced waveform deteriorates, the foot portions of the waveform trail long, and the symmetry of the reproduced waveform is disturbed, and consequently a sufficient equalizing performance cannot be obtained with a cosine equalizer circuit which roughly adjusts the amplitude characteristics only.
As coefficient compensation algorithms capable of obtaining optimum values for a plurality of tap coefficients with relatively high accuracy, sequential compensation type algorithms such as CLMS (clipped least means square) are well known. However, in an apparatus which restores a clock signal for an equalizer circuit from a signal obtained at the subsequent stage of the equalizer circuit, contention occurs between the phase characteristic of the equalizer circuit and clock phase due to tap coefficients of the equalizer becoming asymmetric in the coefficient compensation process, and because of this, the characteristics of the equalizer circuit do not settle. Moreover, a problem arises that the coefficients in the converged state unavoidably oscillate due to the delays of the equalizer circuit and the coefficient compensation circuit portion and also due to the effects of the finite bit number of the digital circuit, and for this reason, a sufficient performance cannot be obtained.
To execute the above-mentioned coefficient compensation operation, the head disk controller needs to cause the read gate to open when the head is located over a data area, and for this purpose at least ID must be able to be read even under a condition that the equalizer circuit is not in the optimized state. Therefore, it is required that a data pattern (a sync byte in this case) to demarcate an area for use with AGC/PLL from a data area be formed in a specific pattern easy to identify.
Furthermore, if a signal processing circuit is designed as a LSI, the scale of the circuit becomes large-size, so it is important to take into consideration the chip area, power consumption, the number of pins. cost, etc. It is desired that all components be packaged in a one-chip LSI. However, if power consumption is large, for instance, the signal processing circuit needs to be formed in two or more subdivided chips and hence it is important at what portion the circuit is to be divided.
An object of the present invention is to provide a high-performance small-scale signal processing circuit, which compensates the amplitude characteristics with high accuracy and also compensates the phase characteristics by a combination of a sequential compensation type coefficient compensation circuit and an equalizer circuit, and provide an information recording/reproducing apparatus using the above-mentioned signal processing circuit.
Another object of the present invention is to provide a method and an apparatus for optimizing various control parameters, which enable the optimization of various control parameters of an information recording/reproducing apparatus in a relatively short time.
Yet another object of the present invention is to provide a more efficient LSI configuration when implementing a reproduced signal processing circuit by subdividing it into LSIs of a plurality of chips.
The above objects of the present invention are achieved by a signal processing circuit including an equalizer circuit and a sequential compensation type coefficient circuit, configured as described in the following.
This signal processing circuit uses a transversal type equalizer circuit with five or more taps, and of the tap coefficients of the equalizer circuit, the tap coefficients adjacent on both sides to the center tap are specified at the same value. Results of simulation by the present inventors showed that when the same value is set for the tap coefficients adjacent on both sides to the center tap, even if the two taps at the extreme ends on both sides are left free, contention with the phase characteristics of the PLL can be avoided, and even if the coefficient compensation circuit is of the sequential compensation type, the coefficient compensation process can proceed stably. The reason is that even when a signal input to the equalizer circuit has a phase distortion, since at least the two coefficients at the extreme end taps on both sides take different values, the waveform distortion after equalization can be minimized.
At this time, the phase distortion of the signal appears as the front-back symmetry Tas of a solitary waveform, and if the Tas is defined as
Tas=T1xe2x88x92T2/PW50
(PW50=T1+T2),
According to the present invention, even when Tas=11%, an equalizing performance substantially equivalent to a Wiener filter (an optimum filter for minimizing the square error) can be obtained. With regard to the symbols in the above equation, PW50 is a mesial point width, the leading edge of PW50 is designated by T1 and the trailing edge is designated by T2. According to the simulation results, if a ratio S of the mesial point width PW50 of a signal input to the equalizer circuit to a data period Tb (this ratio S is called a channel density) is
S=PW50/Tb greater than 2,
the tap number of the equalizer circuit is preferably seven or larger. If the tap number is five, errors are large at the output of the equalizer circuit, so that a good apparatus performance cannot be obtained. In this case, too, of the tap coefficients of the equalizer circuit, only the tap coefficients adjacent on both sides to the center tap are specified at the same value and hence the other four taps on the farther positions on both sides may take different values.
In the present invention, in a transversal type equalizer circuit with five or more taps, of the tap coefficients of the equalizer circuit, not only those adjacent on both sides to the center tap but also those at the positions symmetric with respect to the center tap are preferably, in some cases, at the same value. This is because if there is a good symmetry in the impulse response of signals input to the equalizer circuit, equalization with high accuracy is possible even with a low resolution. Accordingly, in addition to the effect that no contention of phase characteristics occurs as described above, another effect is that coefficient compensation is carried out for all taps by an average or mean correlation signal of two bits at respective tap positions, so that the magnitude of noise of the input signal can be reduced to about 0.7 times the original magnitude and for this reason, coefficient compensation can be performed with good stability.
Further, in the present invention, in an application using a transversal type equalizer circuit, negative coefficient values of the equalizer circuit should preferably be able to be set with positive coefficient values by inverting the output of tap delay means. As in a reproduced waveform of a solitary magnetization in magnetic recording, in the case of a waveform with its foot portions lowering in a relatively monotonous form, the tap coefficients of a transversal type equalizer circuit for equalizing this waveform change their signs alternately in a sequence of minus, plus, minus, plus and so on towards both ends if the sign of the coefficient at the center tap is plus. Therefore, it is possible to output data by inverting data at the tap positions which can be estimated to be negative coefficients. Consequently, the signs of the coefficient bits of the equalizer circuit can be omitted and thus the scale of the circuit can be reduced.
In the present invention, the tap coefficients are preferably set in registers. A coefficient value xe2x80x9c0xe2x80x9d is set at specific tap positions of the transversal type equalizer circuit and the coefficient compensation operation is stopped. By this arrangement, it is possible to perform the most desirable form of coefficient compensation when a small tap number is set, and furthermore power consumption is reduced at the taps with coefficients of xe2x80x9c0xe2x80x9d.
An input signal to the equalizer circuit is preferably input to the coefficient compensation circuit after it is processed into a partial response waveform, for example. By so doing, the accuracy of the coefficient compensation circuit can be improved, coefficient compensation using a rather random, arbitrary data pattern becomes possible, and this compensation operation can be carried out at the user site. For example, even when the characteristics of the magnetic head or disk medium change with time in a magnetic disk apparatus, the optimum equalizer circuit condition can be maintained at all times on the apparatus.
The coefficient compensation of an equalizer circuit according to the present invention is performed by using the following means. To be more specific, the coefficient compensation circuit includes simplified detection means for roughly discriminating an input signal of the equalizer circuit, error calculating means for calculating an error signal from an output signal of the equalizer circuit and the simplified detection means, delay means for delaying the output signal of the simplified detection means, correlation value calculating means for calculating a correlation value between the output signal of the delay means and an output signal of the error calculating means, correlation value adding means for sequentially adding output signals of the correlation value calculating means, delta-value calculation means for calculating a coefficient compensation amount from a signal obtained by adding output signals of the correlation value adding means a certain number of times, and coefficient error compensating means for compensating the coefficient values of the equalizer circuit by an output signal of the coefficient compensation amount calculating means, wherein the coefficient compensation circuit is stopped from performing a sequential addition of correlation values for a delay time after the coefficient compensation is executed until the signal input to the equalizer circuit is output or longer.
According to the above arrangement, correlation data is not obtained while the coefficients are being compensated and the correlation data is accumulated using fixed tap coefficient value at all times. Therefore, the coefficient compensation circuit according to this arrangement does not allow errors to occur which used to occur due to a loop delay in the conventional CLMS (clipped least mean square) step. In addition, this coefficient compensation circuit is basically a open loop and therefore can perform signal processing steps sufficiently, which includes averaging (corresponding to the operation of the correlation value calculating means in this arrangement), and can reduce the effects of the finite bit number or the like, and high hopes can be held on this coefficient compensation circuit for compensation with improved accuracy.
The above-mentioned coefficient compensation circuit may further include delay time control means for controlling the amount of delay of the delay means, selection means for selecting a tap coefficient to be compensated, in an interlocked manner with the delay time control means, and coefficient temporary holding means for temporarily holding a tap coefficient value compensated by the coefficient error compensating means, wherein the delay time may be a fixed amount when the tap coefficient compensation amounts are calculated and all tap coefficients may be compensated when respective tap coefficient values have been decided by controlling the selection means. The coefficient compensation means according to the present invention is formed basically in a open loop, as stated above. Therefore, if it is possible to guarantee the linearity and the randomness of a signal input to the equalizer circuit, respective tap coefficients need not be compensated by the same information (signal). The tap coefficients can be compensated in a time sharing manner, and for this reason the circuit scale can be reduced in a great measure.
Further, in the above-mentioned arrangement, an input signal to the equalizer circuit, which also is an input signal to the coefficient compensation circuit of the equalizer circuit, and an output signal from the equalizer circuit can be input after they are both decimated. As has been described, in the coefficient compensation means, it is only required to receive error signals between an input signal and an output signal of the equalizer circuit, which correspond to the tap coefficients. Therefore, the error signals between the input signal and output signal of the equalizer circuit need not necessarily be obtained continuously, but may be decimated as mentioned above. By decimation, the operation frequency of the coefficient compensation circuit can be reduced to 1/(decimation number+1), so that the power consumption can be reduced to a great extent without increasing the scale of the circuit.
As means for external calculation of the optimum coefficient value, data holding means may be provided to hold, in step with the data clock, signals supplied to the transversal type equalizer circuit for each data segment having at least twice the number of all taps of the equalizer circuit, and output the data held therein by clock means other than the data clock. As for means for obtaining tap coefficients of the equalizer circuit other than the above-mentioned sequential compensation circuit, there is a method of storing a considerable amount of the input signal to the equalizer circuit serially, and giving an ideal output corresponding to the stored input signal to thereby obtain a generally well-known Wiener filter solution. By using this method, it is possible to transfer the stored data to the outside and obtain the optimum solution by a matric operation. The data segment length can be reduced to about twice the number of taps of the equalizer circuit by making contrivance to the data pattern or the like. Note that a longer data segment makes the effects of noise smaller, making it possible to obtain better tap coefficients.
According to the present invention, as a circuit for optimizing the parameters, an error detection circuit can be formed as described in the following.
For example, an error detection circuit includes error calculating means for calculating an error signal in a (second) detection circuit from the input signal supplied to the (second) detection circuit and the output signal from the (second) detection circuit, distinction means for outputting a count signal when an error signal is larger than a preset threshold value; and counting means for counting the count signals. An error signal between the input signal to the detection circuit in the signal processing circuit and the target amplitude of the equalizer circuit is obtained by the (second) detection circuit and the error calculating circuit. This error signal is compared with the fixed threshold value set on the distinction circuit, and when the error signal is equal to or larger than the threshold value, a distinction output is set to xe2x80x9c1xe2x80x9d, or otherwise the distinction output goes to xe2x80x9c0xe2x80x9d. The above-mentioned counting means increments only when the distinction means produces a xe2x80x9c1xe2x80x9d output.
The input signal and the error signal of the above-mentioned detection circuit occur as shown in FIG. 4, and the error signal is distributed over positive and negative sides with xe2x80x9c0xe2x80x9d at the center of distribution and is therefore regarded as substantially a normal distribution. Hence, the ratio of the count value to a total population parameter is decided by the variance value of the error signals and the above-mentioned fixed threshold value of the distinction means. In other words, because the total population parameter and the threshold value are known, the variance value of the error signal can be estimated by the count value. Generally, the performance (BER) of the detection means in the apparatus depends on the quality (the variance value, for example) of signal input to the detection means. Therefore, by minimizing the variance value, the various parameters of the apparatus can be optimized.
In the above-mentioned error detection circuit, the detection level of the (second) detection circuit may be set by using a register. If it is so arranged that the detection level of the (second) detection circuit in the error detection circuit can be set arbitrarily, error detection is possible with the threshold value being varied and this offers the following advantages. Normally, the (second) detection circuit has binary detection levels of +0.5 and xe2x88x920.5 to detect ternary levels of +1, 0 and xe2x88x921. For example, if the output data pattern of the equalizer circuit to be detected is a data pattern which can take only two values of +1 and xe2x88x921, detection errors are likely to occur depending on the magnitude of errors and noise at the above-mentioned detection levels. In this case, if the threshold value is set at xe2x80x9c0xe2x80x9d, the detection circuit can be made to operate as a substantially binary detection circuit, which means that the detection performance is improved (the antinoise performance is improved twice as high) and the error signals can be detected to a more accurate value, so that a more accurate optimization of the apparatus can be achieved.
Further, in the above-mentioned error detection circuit, the detection level of the (second) detection circuit can be set by a register. If the (second) detection circuit can be operated as a binary-output type detection circuit which has one threshold value, the detection performance can be improved (the antinoise performance is improved twice higher than in the prior art) with respect to a specific data pattern and accordingly error signals can be detected to a more accurate value. If the output of the (second) detection circuit is kept at xe2x80x9c0xe2x80x9d at all times, the output value of the equalizer circuit can be input directly to the distinction means.
Further, the above-mentioned error detection circuit may be used along with a register or the like, as described in the following. To give an example, the signal processing circuit may be added with a write current setting register and a write current output terminal. The relation between the write current value of the recording head in an information recording/reproducing apparatus and the amplitude of the reproduced output input to the signal processing circuit is substantially as shown in FIG. 5. Generally, the larger the amplitude of the reproduced output detected by the reproducing head is, the better the quality of the reproduced signal becomes. At this time, if the input signal to the detection means of the signal processing circuit is a signal corresponding to a pattern of . . . +1, +1, xe2x88x921, xe2x88x921, +1, +1 . . . , the typical signal amplitude is made to have only two levels of positive and negative equalization target values by the automatic gain control circuit, providing no level corresponding to xe2x80x9c0xe2x80x9d. Because the ratio of noise to a signal is larger for a smaller reproduced output amplitude, the variance of the error signals input to the distinction means is greater as shown in FIG. 5. Therefore, if the error signals are judged by a suitable negative threshold value and the occasions that an error signal is higher than the threshold value are counted each time the write current value is changed, it will be known that the write current value at which the count value (the number of counts) is greatest is the optimum condition.
According to the present invention, the signal processing circuit may include therein a register to set a sense current value of the reproducing head and a sense current output terminal. When a magnetoresistive effect element is used for the reproducing head of an information recording/reproducing apparatus, if the bias magnetization by the head is not optimized, the amplitude of the reproduced waveform varies depending on the polarity of solitary magnetization. Solitary waveforms are input to the signal processing circuit through AC coupling, the signal to the detection circuit signal shifts with respect to the xe2x80x9c0xe2x80x9d level as shown in FIG. 7. Therefore, data is recorded in a recording pattern such that the magnetization density on the recording medium is lowest, and errors are detected each time the sense current value is changed, as follows.
The output of the (second) detection circuit is maintained at xe2x80x9c0xe2x80x9d at all times, the output of the equalizer circuit is input directly to the distinction means and the threshold value of the distinction means is set at xe2x80x9c0xe2x80x9d, and each time the sense current value is changed, the occasions that the threshold value xe2x80x9c0xe2x80x9d is exceeded for a fixed period of time are counted. When the bias magnetization by the sense current is not optimized and the amplitude ratio varies, the mean value of the error signal shifts from xe2x80x9c0xe2x80x9d, so that the count value does not become xc2xd of a total population parameter. The sense current at which the shift at this time from xe2x80x9c0xe2x80x9d is less than the reference value and the count value obtained by a fixed negative threshold value is greatest is taken as the optimum sense current.
Further, the signal processing circuit may include therein an offset setting circuit for DC offset compensation and an offset compensation register, and the offset amount may be compensated from the no signal condition.
By making arrangement such that the output signal of the equalizer circuit comprises only random circuit noise and detecting errors each time the setting value of the offset compensation amount is changed, the offset compensation amount at which the shift of the mean value of the error signals of equalizer circuit output from xe2x80x9c0xe2x80x9d is smallest is taken as the optimum offset compensation amount.
Note that in a signal processing circuit of the same configuration as mentioned above, the offset amount may be compensated from a single-frequency signal.
By recording data of a single recording frequency and by detecting errors each time the offset compensation amount setting is changed, the offset compensation amount at which the error variance of equalizer circuit output is smallest is taken as the optimum offset compensation amount.
In the present invention, in the signal processing circuit mentioned above, coefficient registers to give desirable characteristics to the equalizer circuit are provided. By using recorded data in a random form and detecting-errors each time the coefficient value setting is changed, the coefficient value at which the error variance of equalizer circuit output is smallest is taken as the optimum offset coefficient value.
A register for a compensation value of the write pre-compensation circuit to compensate the flux reversal positions during recording data according to a sequence of data may be used. By using random data for recording, and detecting errors each time data is recorded with the value setting changed in the compensation value register, the write pre-compensation value at which the error variance of equalizer circuit output is smallest is taken as the optimum compensation value.
In another embodiment of the error detection circuit in the present invention, the error detection circuit may be formed to include distinction means to receive an input signal which is also supplied as an input signal to the detection circuit and output a count signal when the input error-signal is larger than a threshold value; counting means for counting count signals output from the distinction means; and means for setting the threshold value. By arranging such that the output signal of the equalizer circuit (the input signal to the detection circuit) comprises only circuit noise in substantially random form and detecting errors each time the offset compensation amount setting is changed, the offset compensation amount at which the shift of the mean value of the error signals of output of the equalizer circuit from xe2x80x9c0xe2x80x9d is smallest is taken as the optimum offset compensation amount.
Adjustment of the offset compensation value and optimization of the sense current of the magnetoresistive effect type reproducing head can be performed without the (second) detection circuit. A signal processing circuit to enable these operations includes first distinction means for receiving an input signal which is also supplied to the detection circuit and outputting a count signal when the input error signal is less than the threshold value; first counting means for counting count signals from the first distinction means; second distinction means for outputting a count signal when the input error signal is larger than the threshold value; second counting means for counting count signals from the second distinction means; count value calculating means by subtracting the count value of the second counting means from the count value of the first counting means; and means for setting the threshold value.
According to this circuit, by using output signals from the equalizer circuit to directly count errors, it is possible optimize the offset adjustment and the sense current of the magnetoresistive effect type reproducing head.
Note that in this circuit, out of the input signals to the detection circuit, the signals from which sign bits have been removed may be accepted as input signals. If the sign bits are removed from the input signals to the detection circuit (output signals from the equalizer circuit), the negative input signals are converted into positive signals and the originally positive input signals remain unchanged (when the original signals are expressed in 2s compliments). When the output signals of the equalizer circuit are of a single frequency type like +1, +1, xe2x88x921, xe2x88x921, +1, +1, xe2x88x921, xe2x88x921 and so on, the signals from which the sign bits have been removed are converted as shown in FIG. 7. Therefore, by setting the threshold value of the distinction means in the neighborhood of the target value of equalization of the equalizer circuit, the variance of errors can be detected.
Further, in the circuit mentioned above, it is possible to provide two modes; a first mode to accept the signals from which sign bits have been removed out of all input signals to the detection circuit, and a second mode to accept the sign bits too and the two modes can be selected by using registers. This arrangement makes the circuit simpler than in the case where the detection circuit is used, and the offset compensation amount, the write current and the optimum sense current can be obtained by substantially the same method.
Further, to improve the reliability of recording and reproduction of a specific data pattern necessary to optimize the above-mentioned parameters, it is possible to reset the pre-coding means just before a sync byte which indicates the start of a data division when recording data. By so doing, the magnetized condition of the data pattern from the sync byte onwards can be specified, and the specific pattern necessary to optimize the above-mentioned parameters can be recorded.
If the present invention is considered a recording method for causing a flux reversal to occur at data xe2x80x9c1xe2x80x9d and maintaining the write current direction at data xe2x80x9c0xe2x80x9d, such means is used as using a sync byte which starts with xe2x80x9c0xe2x80x9d at the leading end of data and has no successive data xe2x80x9c1xe2x80x9d in a sequence of serial data. By this arrangement, it is possible to provide a sync byte which precludes interference with a data pattern written in advance for the AGC and PLL circuits and provides less chances of non-linear distortion in recording. Therefore, the write current, sense current and equalizer coefficients can be detected with relative ease even if they are not optimized.
Further, in addition to the above arrangement, the sync byte is formed such that the sync byte""s record code data having a sequence of data xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d differs for more than xc2xd of a byte from a sequence of data xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d recorded before the sync byte. Consequently, it is possible to greatly reduce the probability of mistakenly detecting the data pattern for the AGC and PLL circuits written in advance as if it is a sync byte.
Further, in the present invention, to realize a signal processing circuit less subject to degradation, the target amplitude value of an automatic gain control circuit (AGC) is varied according to set values in registers. By this arrangement, when the resolution of input signal is low, by using a smaller target amplitude value, signals are prevented from being saturated in some parts of the signal processing circuit and, for example, impulse noise can be prevented from affecting signal processing. When the resolution of input signal is high, by increasing the target amplitude value, degradation attributable to the circuit such as circuit noise can be reduced and the BER can be improved.
Further, in the present invention, in a signal processing circuit including a mixture of analog and digital circuits, in which the control circuits of the AGC and the PLL are formed as digital circuits, the entire circuit is formed as a two-chip LSI including analog and digital chips, and outputs of the control circuits of the AGC and the PLL on the digital chip are supplied through current-output type D/A converter circuits via pin terminals to a variable gain amplifier (VGA) and a voltage controlled oscillator (VCO) on the analog chip. In this way, by supplying output data from the digital chip in the form of a current, the influence of noise which may enter the signals from the digital chip itself can be reduced, and the number of pins required can be made substantially smaller than in the case where those signals are output in the form of a digital signal of several-bit codes.